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1/26 september 2002 M48T08 M48T08y, m48t18 5v, 64 kbit (8 kb x 8) timekeeper ? sram features summary n integrated ultra low power sram, real time clock, power-fail control circuit, and battery n bytewide? ram-like clock access n bcd coded year, month, day, date, hours, minutes, and seconds n typical clock accuracy of 1 minute a month, at 25c n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C M48T08: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C m48t18/t08y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v n software controlled clock calibration for high accuracy applications n self-contained battery and crystal in the caphat? dip package n packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat top which contains the battery and crystal n pin and function compatible with ds1643 and jedec standard 8k x 8 srams figure 1. 28-pin pcdip, caphat? package figure 2. 28-pin soic package 28 1 pcdip28 (pc) battery/crystal caphat 28 1 snaphat (sh) battery/crystal soh28 (mh)
M48T08, m48t18, M48T08y 2/26 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 logic diagram (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 dip connections (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 soic connections (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ac testing load circuit (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating modes (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode ac waveforms (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable controlled, write ac waveform (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chip enable controlled, write ac waveforms (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 write mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up mode ac waveforms (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up ac characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power down/up trip points dc characteristics (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register map (table 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 crystal accuracy across temperature (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 clock calibration (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 supply voltage protection (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 snaphat battery table (table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26 M48T08, m48t18, M48T08y summary description the M48T08/18/08y timekeeper ? ram is an 8k x 8 non-volatile static ram and real time clock which is pin and functional compatible with the ds1643. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock so- lution. the M48T08/18/08y is a non-volatile pin and func- tion equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600mil dip caphat? houses the M48T08/18/08y silicon with a quartz crystal and a long- life lithium button cell in a single package. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. inser- tion of the snaphat housing after reflow pre- vents potential battery and crystal damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28 lead soic, the bat- tery/crystal package (e.g., snaphat) part num- ber is m4t28-br12sh or m4t32-br12sh (see table 13, page 20). figure 3. logic diagram table 1. signal names ai01020 13 a0-a12 w dq0-dq7 v cc M48T08 M48T08y m48t18 g e2 v ss 8 e1 int a0-a12 address inputs dq0-dq7 data inputs / outputs int power fail interrupt (open drain) e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground
M48T08, m48t18, M48T08y 4/26 figure 4. dip connections figure 5. soic connections figure 6. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc ai01182 M48T08 m48t18 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 ai01021b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc M48T08y ai01333 lithium cell oscillator and clock chain v pfd int v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 8184 x 8 sram array a0-a12 dq0-dq7 e1 e2 w g power
5/26 M48T08, m48t18, M48T08y maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
M48T08, m48t18, M48T08y 6/26 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac testing load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M48T08 m48t18/t08y unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
7/26 M48T08, m48t18, M48T08y table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. outputs deselected. 3. measured with control bits set as follows: r = '1'; w, st, ft = '0.' 4. negative spikes of C1v allowed for up to 10ns once per cycle. 5. the int pin is open drain. symbol parameter test condition (1) M48T08/m48t18/t08y unit min max i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 (3) supply current (standby) ttl e1 = v ih, e2 = v il 3ma i cc2 (3) supply current (standby) cmos e1 = v cc C 0.2v, e2 = v ss + 0.2v 3ma v il (4) input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v output low voltage (int ) (5) i ol = 0.5ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v
M48T08, m48t18, M48T08y 8/26 operation modes as figure 6, page 4 shows, the static memory ar- ray and the quartz-controlled clock oscillator of the M48T08/18/08y are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 1ff8h-1fffh. the clock locations contain the year, month, date, day, hour, minute, and second in 24 hour bcd for- mat. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automat- ically. byte 1ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the M48T08/18/08y includes a clock control circuit which updates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the M48T08/18/08y also has its own power-fail detect circuit. the control circuitry constantly mon- itors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc . as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operation until val- id power returns. table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 10, page 15 for details. mode v cc e1 e2 g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v v ih x x x high z standby deselect x v il x x high z standby write v il v ih x v il d in active read v il v ih v il v ih d out active read v il v ih v ih v ih high z active deselect v so to v pfd (min) (1) x x x x high z cmos standby deselect v so (1) x x x x high z battery back-up mode
9/26 M48T08, m48t18, M48T08y read mode the M48T08/18/08y is in the read mode when- ever w (write enable) is high, e1 (chip enable 1) is low, and e2 (chip enable 2) is high. the de- vice architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e1 , e2, and g access times are also satisfied. if the e1 , e2 and g access times are not met, valid data will be available after the latter of the chip enable access times (t e1lqv or t e2hqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e1 , e2 and g . if the outputs are ac- tivated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e1 , e2 and g remain ac- tive, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 8. read mode ac waveforms note: write enable (w ) = high. ai00962 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a12 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2
M48T08, m48t18, M48T08y 10/26 table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). symbol parameter (1) M48T08/m48t18/t08y unit C100/C10 (t08y) C150/C15 (t08y) min max min max t avav read cycle time 100 150 ns t avqv address valid to output valid 100 150 ns t e1lqv chip enable 1 low to output valid 100 150 ns t e2hqv chip enable 2 high to output valid 100 150 ns t glqv output enable low to output valid 50 75 ns t e1lqx chip enable 1 low to output transition 10 10 ns t e2hqx chip enable 2 high to output transition 10 10 ns t glqx output enable low to output transition 5 5 ns t e1hqz chip enable 1 high to output hi-z 50 75 ns t e2lqz chip enable 2 low to output hi-z 50 75 ns t ghqz output enable high to output hi-z 40 60 ns t axqx address transition to output transition 5 5 ns
11/26 M48T08, m48t18, M48T08y write mode the M48T08/18/08y is in the write mode when- ever w , e1 , and e2 are active. the start of a write is referenced from the latter occurring fall- ing edge of w or e1 , or the rising edge of e2. a write is terminated by the earlier rising edge of w or e1 , or the falling edge of e2. the addresses must be held valid throughout the cycle. e1 or w must return high or e2 low for a minimum of t e1hax or t e2lax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx af- terward. g should be kept high during write cy- cles to avoid bus contention; however, if the output bus has been activated by a low on e1 and g and a high on e2, a low on w will disable the outputs t wlqz after w falls. figure 9. write enable controlled, write ac waveform ai00963 tavav twhax tdvwh data input a0-a12 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx
M48T08, m48t18, M48T08y 12/26 figure 10. chip enable controlled, write ac waveforms ai00964b tavav te1hax tdve1h tdve2l a0-a12 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input
13/26 M48T08, m48t18, M48T08y table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). symbol parameter (1) M48T08/m48t18/t08y unit C100/C10 (t08y) C150/C15 (t08y) min max min max t avav write cycle time 100 150 ns t av wl address valid to write enable low 0 0 ns t av e1l address valid to chip enable 1 low 0 0 ns t ave2h address valid to chip enable 2 high 0 0 ns t wlwh write enable pulse width 80 100 ns t e1le1h chip enable 1 low to chip enable 1 high 80 130 ns t e2he2l chip enable 2 high to chip enable 2 low 80 130 ns t whax write enable high to address transition 10 10 ns t e1hax chip enable 1 high to address transition 10 10 ns t e2lax chip enable 2 low to address transition 10 10 ns t dvwh input valid to write enable high 50 70 ns t dve1h input valid to chip enable 1 high 50 70 ns t dve2l input valid to chip enable 2 low 50 70 ns t whdx write enable high to input transition 5 5 ns t e1hdx chip enable 1 high to input transition 5 5 ns t e2ldx chip enable 2 low to input transition 5 5 ns t wlqz write enable low to output hi-z 50 70 ns t avwh address valid to write enable high 80 130 ns t ave1h address valid to chip enable 1 high 80 130 ns t av e2l address valid to chip enable 2 low 80 130 ns t whqx write enable high to output transition 10 10 ns
M48T08, m48t18, M48T08y 14/26 data retention mode with valid v cc applied, the M48T08/18/08y oper- ates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the M48T08/18/08y may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the M48T08/18/ 08y for an accumulated period of at least 10 years when v cc is less than v so . note: requires use of m4t32-br12sh snaphat ? top when using the soh28 package. as system power returns and v cc rises above v so , the battery is disconnected and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). e1 should be kept high or e2 low as v cc rises past v pfd (min) to prevent inad- vertent write cycles prior to system stab ilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. power-fail interrupt pin the M48T08/18/08y continuously monitors v cc . when v cc falls to the power-fail detect trip point, an interrupt is immediately generated. an internal clock provides a delay of between 10s and 40s before automatically deselecting the M48T08/18/ 08y. the int pin is an open drain output and re- quires an external pull up resistor, even if the inter- rupt output function is not being used. figure 11. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e1 high or e2 low as v cc rises past v pfd (min). some systems may perform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. ai00566 v cc inputs int (per control input) outputs don't care high-z tf tfb tpfx tr tpfh trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so
15/26 M48T08, m48t18, M48T08y table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 3. at 55c; t dr = 8.5 years (typ) at 70c. requires use of m4t32-br12sh snaphat ? top when using the soh28 package. symbol parameter (1) min max unit t pd e1 or w at v ih or e2 at v il before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0s t rb v ss to v pfd (min) v cc rise time 1s t rec e1 or w at v ih or e2 at v il before power up 1ms t pfx int low to auto deselect 10 40 s t pfh v pfd (max) to int high 120 s symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage M48T08 4.5 4.6 4.75 v m48t18/t08y 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr expected data retention time 10 (3) years
M48T08, m48t18, M48T08y 16/26 clock operations reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, the seventh bit in the control register. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' setting the clock the eighth bit of the control register is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the time keeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (on ta- ble 11). resetting the write bit to a '0' then trans- fers the values of all time registers (1ff9h-1fffh) to the actual timekeeper counters and allows normal operation to resume. the ft bit and the bits marked as '0' in table 11 must be written to '0' to allow for normal timekeeper and ram oper- ation. see the application note an923, timek eeper ? rolling into the 21 st century for information on century rollover. table 11. register map keys: s = sign bit ft = frequency test bit (set to '0' for normal clock operation) r = read bit w = write bit st = stop bit 0 = must be set to '0' address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m month month 01-12 1ffdh 0 0 10 date date date 01-31 1ffch 0 ft 0 0 0 day day 01-07 1ffbh 0 0 10 hours hours hours 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control
17/26 M48T08, m48t18, M48T08y stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit (st) is the msb of the seconds register. setting it to a '1' stops the oscillator. the M48T08/18/08y (in the pcdip28 package) is shipped from stmi- croelectronics with the stop bit set to a '1.' when reset to a '0,' the M48T08/18/08y oscillator starts within one second. note: to guarantee oscillator start-up after initial power-up, first write the stop bit (st) to '1,' then reset to '0.' calibrating the clock the M48T08/18/08y is driven by a quartz-con- trolled oscillator with a nominal frequency of 32,768 hz. a typical M48T08/18/08y is accurate within 1 minute per month at 25c without calibra- tion. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each M48T08/18/08y improves to better than +1/C2 ppm at 25c. the oscillation rate of any crystal changes with temperature. figure 12, page 18 shows the fre- quency error that can be expected at various tem- peratures. most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the M48T08/18/ 08y design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 13, page 18. the number of times pulses are blanked (subtract- ed, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is the sign bit; '1' indicates pos- itive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given M48T08/18/08y may re- quire. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the fi- nal product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of standard test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 hz, the lsb (dq0) of the sec- onds register will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would in- dicate a +20 ppm oscillator frequency error, re- quiring a C10 (wr001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output fre- quency. the device must be selected and ad- dresses must be stable at address 1ff9h when reading the 512 hz on dq0. the ft bit must be set using the same method used to set the clock: using the write bit. the lsb of the seconds register is monitored by hold- ing the M48T08/18/08y in an extended read of the seconds register, but without having the read bit set. the ft bit must be reset to '0' for normal clock operations to resume. for more information on calibration, see the appli- cation note an934, timek eeper ? calibration.
M48T08, m48t18, M48T08y 18/26 figure 12. crystal accuracy across temperature figure 13. clock calibration ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal positive calibration negative calibration
19/26 M48T08, m48t18, M48T08y v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 14) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 14. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
M48T08, m48t18, M48T08y 20/26 part numbering table 12. ordering information scheme note: 1. the M48T08/18 part is offered with the pcdip28 (e.g., caphat?) package only. 2. the soic package (soh28) requires the battery/crystal package (snaphat ? ) which is ordered separately under the part number m4txx-br12sh in plastic tube or m4txx-br12shtr in tape & reel form. the M48T08y part is offered in the soh28 (snaphat) package only. caution : do not place the snaphat battery package m4txx-br12sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. table 13. snaphat battery table example: m48t 18 C100 pc 1 tr device type m48t supply voltage and write protect voltage 08 (1) = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 18/08y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v speed C100 = 100ns C150 = 150ns C10 = 100ns (M48T08y) package pc (1) = pcdip28 mh (2) = soh28 temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
21/26 M48T08, m48t18, M48T08y package mechanical information figure 15. pcdip28 C 28-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 14. pcdip28 C 28-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
M48T08, m48t18, M48T08y 22/26 figure 16. soh28 C 28-lead plastic small outline, 4-socket battery snaphat, package outline note: drawing is not to scale. table 15. soh28 C 28-lead plastic small outline, 4-socket battery snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n 28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
23/26 M48T08, m48t18, M48T08y figure 17. sh C 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 16. sh C 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
M48T08, m48t18, M48T08y 24/26 figure 18. sh C 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 17. sh C 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
25/26 M48T08, m48t18, M48T08y revision history table 18. document revision history date rev. # revision details december 1999 1.0 first issue 02/07/00 2.0 from preliminary data to data sheet; battery low flag paragraph changed; 100ns speed class identifier changed (tables 7, 8) 07/11/00 2.1 t fb changed (table 9); watchdog timer paragraph changed 07/16/01 3.0 reformatted; snaphat battery table added (table 13); added temp./voltage info. to tables (tables 4, 5, 7, 8, 9, 10) 08/01/01 3.1 reference to app. note corrected in calibrating the clock section 12/21/01 3.2 changes to text in document to reflect addition of M48T08y option 03/06/02 3.3 fix ordering information table and add to footnote (table 12) 05/20/02 3.4 modify reflow time and temperature footnotes (table 2) 08/29/02 3.5 t dr specification temperature updated (table 10)
M48T08, m48t18, M48T08y 26/26 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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